Sampada Barve, Sithara Raveendran, Charudatta Korde, Trilochan Panigrahi, Nithin Y. B. Kumar, M. H. Vasantha. FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics. In IEEE International Symposium on Smart Electronic Systems, iSES 2018 (Formerly iNiS), Hyderabad, India, December 17-19, 2018. pages 6-10, IEEE, 2018. [doi]
@inproceedings{BarveRKPKV18,
title = {FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics},
author = {Sampada Barve and Sithara Raveendran and Charudatta Korde and Trilochan Panigrahi and Nithin Y. B. Kumar and M. H. Vasantha},
year = {2018},
doi = {10.1109/iSES.2018.00012},
url = {https://doi.org/10.1109/iSES.2018.00012},
researchr = {https://researchr.org/publication/BarveRKPKV18},
cites = {0},
citedby = {0},
pages = {6-10},
booktitle = {IEEE International Symposium on Smart Electronic Systems, iSES 2018 (Formerly iNiS), Hyderabad, India, December 17-19, 2018},
publisher = {IEEE},
isbn = {978-1-5386-9172-4},
}