Estimating design time for system circuits

Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, Jose Renau. Estimating design time for system circuits. In IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007. pages 60-65, IEEE, 2007. [doi]

Abstract

Abstract is missing.