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2 GB/S decision feedback equalizer in 3.3 V 0.35 µM CMOS

Håkan Bengtson, Christer Svensson. 2 GB/S decision feedback equalizer in 3.3 V 0.35 µM CMOS. In M. H. Rashid, editor, Proceedings of the Second IASTED International Conference on Circuits, Signals, and Systems, Clearwater Beach, FL, USA, November 28, 2004 - December 1, 2004. pages 114-119, IASTED/ACTA Press, 2004.

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