Anna Bernasconi, Valentina Ciriani. Logic synthesis and testability of D-reducible functions. In 18th IEEE/IFIP VLSI-SoC 2010, IEEE/IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Madrid, Spain, 27-29 September 2010. pages 280-285, IEEE, 2010. [doi]
@inproceedings{BernasconiC10,
title = {Logic synthesis and testability of D-reducible functions},
author = {Anna Bernasconi and Valentina Ciriani},
year = {2010},
doi = {10.1109/VLSISOC.2010.5642674},
url = {http://dx.doi.org/10.1109/VLSISOC.2010.5642674},
tags = {testing, logic},
researchr = {https://researchr.org/publication/BernasconiC10},
cites = {0},
citedby = {0},
pages = {280-285},
booktitle = {18th IEEE/IFIP VLSI-SoC 2010, IEEE/IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Madrid, Spain, 27-29 September 2010},
publisher = {IEEE},
}