A design environment with simulation and formal verification (syr-padde)

Miquel Bertran, Felipe Alvarez-Cuevas, Joan Viaplana, Albert Duran, Daniel Cabedo, Antoni Garrell, Josep M. Garrell, Francesc Escudero, Miquel Nicolau, Miquel Porta, Bartomeu Palmer, Joan M. Espejo, Frances Oller, Jordi Forga, Josep M. Solanas. A design environment with simulation and formal verification (syr-padde). In Fifth IEEE International Workshop on Computer-Aided Modeling, Analysis, and Design of Communication Links and Networks, CAMAD '94, Princeton, NJ, USA, April 24-27, 1994. IEEE, 1994. [doi]

Abstract

Abstract is missing.