Luca Bertulessi, Saleh Karman, Dmytro Cherniak, Alessandro Garghetti, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino. A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS. J. Solid-State Circuits, 54(12):3493-3502, 2019. [doi]
@article{BertulessiKCGSL19,
title = {A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS},
author = {Luca Bertulessi and Saleh Karman and Dmytro Cherniak and Alessandro Garghetti and Carlo Samori and Andrea L. Lacaita and Salvatore Levantino},
year = {2019},
doi = {10.1109/JSSC.2019.2940332},
url = {https://doi.org/10.1109/JSSC.2019.2940332},
researchr = {https://researchr.org/publication/BertulessiKCGSL19},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {54},
number = {12},
pages = {3493-3502},
}