An FPGA-based irrational decimator for digital receivers

Amir Beygi, Ali Mohammadi, Adib Abrishamifar. An FPGA-based irrational decimator for digital receivers. In 9th International Symposium on Signal Processing and Its Applications, ISSPA 2007, Sharjah, United Arab Emirates, February 12-15, 2007. pages 1-4, IEEE, 2007. [doi]

@inproceedings{BeygiMA07,
  title = {An FPGA-based irrational decimator for digital receivers},
  author = {Amir Beygi and Ali Mohammadi and Adib Abrishamifar},
  year = {2007},
  doi = {10.1109/ISSPA.2007.4555382},
  url = {http://dx.doi.org/10.1109/ISSPA.2007.4555382},
  researchr = {https://researchr.org/publication/BeygiMA07},
  cites = {0},
  citedby = {0},
  pages = {1-4},
  booktitle = {9th International Symposium on Signal Processing and Its Applications, ISSPA 2007, Sharjah, United Arab Emirates, February 12-15, 2007},
  publisher = {IEEE},
  isbn = {1-4244-0779-6},
}