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Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations

Sarvesh Bhardwaj, Sarma B. K. Vrudhula. Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems, 27(3):445-455, 2008. [doi]

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