Test method and scheme for low-power validation in modern SOC integrated circuits - researchr publication authors

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Bonita Bhaskaran, Amit Sanghani, Kaushik Narayanun, Ayub Abdollahian, Amit Laknaur. Test method and scheme for low-power validation in modern SOC integrated circuits. In 34th IEEE VLSI Test Symposium, VTS 2016, Las Vegas, NV, USA, April 25-27, 2016. pages 1-6, IEEE Computer Society, 2016. [doi]

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