Ameya Bhide, Atila Alvandpour. Timing challenges in high-speed interleaved ΔΣ DACs. In 2014 International Symposium on Integrated Circuits (ISIC), Singapore, December 10-12, 2014. pages 46-49, IEEE, 2014. [doi]
@inproceedings{BhideA14,
title = {Timing challenges in high-speed interleaved ΔΣ DACs},
author = {Ameya Bhide and Atila Alvandpour},
year = {2014},
doi = {10.1109/ISICIR.2014.7029513},
url = {http://dx.doi.org/10.1109/ISICIR.2014.7029513},
researchr = {https://researchr.org/publication/BhideA14},
cites = {0},
citedby = {0},
pages = {46-49},
booktitle = {2014 International Symposium on Integrated Circuits (ISIC), Singapore, December 10-12, 2014},
publisher = {IEEE},
isbn = {978-1-4799-4833-8},
}