Effect of Clock Duty-Cycle Error on Two-Channel Interleaved ΔΣ DACs

Ameya Bhide, Amin Ojani, Atila Alvandpour. Effect of Clock Duty-Cycle Error on Two-Channel Interleaved ΔΣ DACs. IEEE Trans. on Circuits and Systems, 62-II(7):646-650, 2015. [doi]

Abstract

Abstract is missing.