A hardware-efficient variable-length FFT processor for low-power applications

Yifan Bo, Renfeng Dou, Jun Han, Xiaoyang Zeng. A hardware-efficient variable-length FFT processor for low-power applications. In Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA 2013, Kaohsiung, Taiwan, October 29 - November 1, 2013. pages 1-4, IEEE, 2013. [doi]

Authors

Yifan Bo

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Renfeng Dou

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Jun Han

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Xiaoyang Zeng

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