Yifan Bo, Renfeng Dou, Jun Han, Xiaoyang Zeng. A hardware-efficient variable-length FFT processor for low-power applications. In Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA 2013, Kaohsiung, Taiwan, October 29 - November 1, 2013. pages 1-4, IEEE, 2013. [doi]
@inproceedings{BoDHZ13,
title = {A hardware-efficient variable-length FFT processor for low-power applications},
author = {Yifan Bo and Renfeng Dou and Jun Han and Xiaoyang Zeng},
year = {2013},
doi = {10.1109/APSIPA.2013.6694120},
url = {http://dx.doi.org/10.1109/APSIPA.2013.6694120},
researchr = {https://researchr.org/publication/BoDHZ13},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA 2013, Kaohsiung, Taiwan, October 29 - November 1, 2013},
publisher = {IEEE},
isbn = {978-1-4799-2794-4},
}