Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction

Ashish Reddy Bommana, Susheel Ujwal Siddamshetty, Pudi Dhilleswararao, Arvind Thumatti K. R., Srinivas Boppu, M. Sabarimalai Manikandan, Linga Reddy Cenkeramaddi. Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction. ACM Trans. Design Autom. Electr. Syst., 28(3), 2023. [doi]

Abstract

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