Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random V::T:: Variations on Timing - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici. Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random V::T:: Variations on Timing. In René van Leuken, Gilles Sicard, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers. Volume 6448 of Lecture Notes in Computer Science, pages 170-179, Springer, 2010. [doi]

This author has not been identified. Look up 'Bahman Kheradmand Boroujeni' in GoogleThis author has not been identified. Look up 'Christian Piguet' in GoogleThis author has not been identified. Look up 'Yusuf Leblebici' in Google

runs on WebDSL