Formal Verification of VHDL Descriptions in the Prevail Environment

Dominique Borrione, Laurence V. Pierre, Ashraf M. Salem. Formal Verification of VHDL Descriptions in the Prevail Environment. IEEE Design & Test of Computers, 9(2):42-56, 1992. [doi]

@article{BorrionePS92,
  title = {Formal Verification of VHDL Descriptions in the Prevail Environment},
  author = {Dominique Borrione and Laurence V. Pierre and Ashraf M. Salem},
  year = {1992},
  doi = {10.1109/54.143145},
  url = {http://doi.ieeecomputersociety.org/10.1109/54.143145},
  tags = {meta-model, Meta-Environment, meta-objects},
  researchr = {https://researchr.org/publication/BorrionePS92},
  cites = {0},
  citedby = {0},
  journal = {IEEE Design & Test of Computers},
  volume = {9},
  number = {2},
  pages = {42-56},
}