Verification of Asynchronous Circuits using Timed Automata

Marius Bozga, Hou Jianmin, Oded Maler, Sergio Yovine. Verification of Asynchronous Circuits using Timed Automata. Electronic Notes in Theoretical Computer Science, 65(6):47-59, 2002. [doi]

@article{BozgaJMY02,
  title = {Verification of Asynchronous Circuits using Timed Automata},
  author = {Marius Bozga and Hou Jianmin and Oded Maler and Sergio Yovine},
  year = {2002},
  url = {http://www.elsevier.com/gej-ng/31/29/23/117/51/show/Products/notes/index.htt#005},
  researchr = {https://researchr.org/publication/BozgaJMY02},
  cites = {0},
  citedby = {0},
  journal = {Electronic Notes in Theoretical Computer Science},
  volume = {65},
  number = {6},
  pages = {47-59},
}