P. Branchini, A. Fabbh, D. Riondino, Luigi Mariucci, Matteo Rapisarda, Antonio Valletta, A. Aloisio, F. Di Capua. Logic gates and memory elements design and simulation using PMOS organic transistor. In IEEE 26th International Symposium on Industrial Electronics, ISIE 2017, Edinburgh, United Kingdom, June 19-21, 2017. pages 2097-2101, IEEE, 2017. [doi]
@inproceedings{BranchiniFRMRVA17,
title = {Logic gates and memory elements design and simulation using PMOS organic transistor},
author = {P. Branchini and A. Fabbh and D. Riondino and Luigi Mariucci and Matteo Rapisarda and Antonio Valletta and A. Aloisio and F. Di Capua},
year = {2017},
doi = {10.1109/ISIE.2017.8001580},
url = {https://doi.org/10.1109/ISIE.2017.8001580},
researchr = {https://researchr.org/publication/BranchiniFRMRVA17},
cites = {0},
citedby = {0},
pages = {2097-2101},
booktitle = {IEEE 26th International Symposium on Industrial Electronics, ISIE 2017, Edinburgh, United Kingdom, June 19-21, 2017},
publisher = {IEEE},
isbn = {978-1-5090-1412-5},
}