Potential analysis of a superscalar core employing a reconfigurable array for improving instruction-level parallelism

Marcelo Brandalero, Antonio Carlos Schneider Beck. Potential analysis of a superscalar core employing a reconfigurable array for improving instruction-level parallelism. Design Autom. for Emb. Sys., 20(2):155-169, 2016. [doi]

Abstract

Abstract is missing.