A 17 × 69 bit multiply and add unit with redundant binary feedback and single cycle latency - researchr publication authors

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W. S. Briggs, David W. Matula. A 17 × 69 bit multiply and add unit with redundant binary feedback and single cycle latency. In Earl E. Swartzlander Jr., Mary Jane Irwin, Graham A. Jullien, editors, 11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings. pages 163-170, IEEE Computer Society/, 1993. [doi]

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