Mike Brinson. FOSS Compact Model Prototyping with Verilog-A Equation-Defined Devices (VAEDD). In Andrzej Napieralksi, editor, 26th International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES 2019, Rzeszów, Poland, June 27-29, 2019. pages 92-97, IEEE, 2019. [doi]
@inproceedings{Brinson19,
title = {FOSS Compact Model Prototyping with Verilog-A Equation-Defined Devices (VAEDD)},
author = {Mike Brinson},
year = {2019},
doi = {10.23919/MIXDES.2019.8787063},
url = {https://doi.org/10.23919/MIXDES.2019.8787063},
researchr = {https://researchr.org/publication/Brinson19},
cites = {0},
citedby = {0},
pages = {92-97},
booktitle = {26th International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES 2019, Rzeszów, Poland, June 27-29, 2019},
editor = {Andrzej Napieralksi},
publisher = {IEEE},
isbn = {978-83-63578-16-9},
}