FOSS Compact Model Prototyping with Verilog-A Equation-Defined Devices (VAEDD)

Mike Brinson. FOSS Compact Model Prototyping with Verilog-A Equation-Defined Devices (VAEDD). In Andrzej Napieralksi, editor, 26th International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES 2019, Rzeszów, Poland, June 27-29, 2019. pages 92-97, IEEE, 2019. [doi]

Abstract

Abstract is missing.