Javier D. Bruguera, Tomás Lang. Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition. In 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 27-29 June 2005, Cape Cod, MA, USA. pages 42-51, IEEE Computer Society, 2005. [doi]
@inproceedings{BrugueraL05,
title = {Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition},
author = {Javier D. Bruguera and Tomás Lang},
year = {2005},
doi = {10.1109/ARITH.2005.22},
url = {http://doi.ieeecomputersociety.org/10.1109/ARITH.2005.22},
researchr = {https://researchr.org/publication/BrugueraL05},
cites = {0},
citedby = {0},
pages = {42-51},
booktitle = {17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 27-29 June 2005, Cape Cod, MA, USA},
publisher = {IEEE Computer Society},
isbn = {0-7695-2366-8},
}