Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition - researchr publication

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Javier D. Bruguera, Tomás Lang. Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition. In 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 27-29 June 2005, Cape Cod, MA, USA. pages 42-51, IEEE Computer Society, 2005. [doi]

Abstract is missing.

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