Gianpiero Cabodi, Paolo Camurati, Marco Palena, P. Pasini, Danilo Vendraminetto. Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening. In Ruzica Piskac, Muralidhar Talupur, editors, 2016 Formal Methods in Computer-Aided Design, FMCAD 2016, Mountain View, CA, USA, October 3-6, 2016. pages 25-32, IEEE, 2016. [doi]
@inproceedings{CabodiCPPV16,
title = {Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening},
author = {Gianpiero Cabodi and Paolo Camurati and Marco Palena and P. Pasini and Danilo Vendraminetto},
year = {2016},
doi = {10.1109/FMCAD.2016.7886657},
url = {http://dx.doi.org/10.1109/FMCAD.2016.7886657},
researchr = {https://researchr.org/publication/CabodiCPPV16},
cites = {0},
citedby = {0},
pages = {25-32},
booktitle = {2016 Formal Methods in Computer-Aided Design, FMCAD 2016, Mountain View, CA, USA, October 3-6, 2016},
editor = {Ruzica Piskac and Muralidhar Talupur},
publisher = {IEEE},
isbn = {978-0-9835678-6-8},
}