Gianpiero Cabodi, Paolo Camurati, Marco Palena, P. Pasini, Danilo Vendraminetto. Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening. In Ruzica Piskac, Muralidhar Talupur, editors, 2016 Formal Methods in Computer-Aided Design, FMCAD 2016, Mountain View, CA, USA, October 3-6, 2016. pages 25-32, IEEE, 2016. [doi]
Abstract is missing.