FPGA implementation of layered low density parity check error correction codes

Abdulsamet Caglan, Ersen Balcisoy, Emre Kirkaya, Gurbannazar Charyyev, Adem Çiçek, Enver Cavus. FPGA implementation of layered low density parity check error correction codes. In 25th Signal Processing and Communications Applications Conference, SIU 2017, Antalya, Turkey, May 15-18, 2017. pages 1-4, IEEE, 2017. [doi]

Abstract

Abstract is missing.