Hao Cai, Zhong-Jian Bian, Yaoru Hou, Yongliang Zhou, Jia-Le Cui, Yanan Guo, Xiaoyun Tian, Bo Liu 0019, Xin Si, Zhen Wang, Jun Yang 0006, Weiwei Shan. A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference. In IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023. pages 500-501, IEEE, 2023. [doi]
@inproceedings{CaiBHZCGTLSWYS23,
title = {A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference},
author = {Hao Cai and Zhong-Jian Bian and Yaoru Hou and Yongliang Zhou and Jia-Le Cui and Yanan Guo and Xiaoyun Tian and Bo Liu 0019 and Xin Si and Zhen Wang and Jun Yang 0006 and Weiwei Shan},
year = {2023},
doi = {10.1109/ISSCC42615.2023.10067339},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067339},
researchr = {https://researchr.org/publication/CaiBHZCGTLSWYS23},
cites = {0},
citedby = {0},
pages = {500-501},
booktitle = {IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023},
publisher = {IEEE},
isbn = {978-1-6654-9016-0},
}