Efficient Check Node Processing Architectures for Non-binary LDPC Decoding Using Power Representation

Fang Cai, Xinmiao Zhang. Efficient Check Node Processing Architectures for Non-binary LDPC Decoding Using Power Representation. VLSI Signal Processing, 76(2):211-222, 2014. [doi]

@article{CaiZ14-0,
  title = {Efficient Check Node Processing Architectures for Non-binary LDPC Decoding Using Power Representation},
  author = {Fang Cai and Xinmiao Zhang},
  year = {2014},
  doi = {10.1007/s11265-013-0864-x},
  url = {http://dx.doi.org/10.1007/s11265-013-0864-x},
  researchr = {https://researchr.org/publication/CaiZ14-0},
  cites = {0},
  citedby = {0},
  journal = {VLSI Signal Processing},
  volume = {76},
  number = {2},
  pages = {211-222},
}