Sub-threshold Circuit Design with Shrinking CMOS Devices

Benton H. Calhoun, Sudhanshu Khanna, Randy W. Mann, Jiajing Wang. Sub-threshold Circuit Design with Shrinking CMOS Devices. In International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan. pages 2541-2544, IEEE, 2009. [doi]

@inproceedings{CalhounKMW09,
  title = {Sub-threshold Circuit Design with Shrinking CMOS Devices},
  author = {Benton H. Calhoun and Sudhanshu Khanna and Randy W. Mann and Jiajing Wang},
  year = {2009},
  doi = {10.1109/ISCAS.2009.5118319},
  url = {http://dx.doi.org/10.1109/ISCAS.2009.5118319},
  tags = {design},
  researchr = {https://researchr.org/publication/CalhounKMW09},
  cites = {0},
  citedby = {0},
  pages = {2541-2544},
  booktitle = {International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan},
  publisher = {IEEE},
}