Antonio Martí Campoy, Francisco Rodríguez-Ballester. Combining watchdog processor with instruction cache locking for a fault-tolerant, predictable architecture applied to fixed-priority, preemptive, multitasking real-time systems. In 24th IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2019, Zaragoza, Spain, September 10-13, 2019. pages 259-265, IEEE, 2019. [doi]
@inproceedings{CampoyR19,
title = {Combining watchdog processor with instruction cache locking for a fault-tolerant, predictable architecture applied to fixed-priority, preemptive, multitasking real-time systems},
author = {Antonio Martí Campoy and Francisco Rodríguez-Ballester},
year = {2019},
doi = {10.1109/ETFA.2019.8869168},
url = {https://doi.org/10.1109/ETFA.2019.8869168},
researchr = {https://researchr.org/publication/CampoyR19},
cites = {0},
citedby = {0},
pages = {259-265},
booktitle = {24th IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2019, Zaragoza, Spain, September 10-13, 2019},
publisher = {IEEE},
isbn = {978-1-7281-0303-7},
}