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Combining watchdog processor with instruction cache locking for a fault-tolerant, predictable architecture applied to fixed-priority, preemptive, multitasking real-time systems

Antonio Martí Campoy, Francisco Rodríguez-Ballester. Combining watchdog processor with instruction cache locking for a fault-tolerant, predictable architecture applied to fixed-priority, preemptive, multitasking real-time systems. In 24th IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2019, Zaragoza, Spain, September 10-13, 2019. pages 259-265, IEEE, 2019. [doi]

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