IP Validation for FPGAs using Hardware Object Technology:::TM:::

Steve Casselman, John Schewel, Christophe Beaumont. IP Validation for FPGAs using Hardware Object Technology:::TM:::. In 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP 99), 12-16 April 1999, San Juan, Puerto Rico, Proceedings. pages 624, IEEE Computer Society, 1999. [doi]

Abstract

Abstract is missing.