Andrew S. Cassidy, John V. Arthur, Filipp Akopyan, Alexander Andreopoulos, Rathinakumar Appuswamy, Pallab Datta, Michael V. DeBole, Steven K. Esser, Carlos Ortega-Otero, Jun Sawada, Brian Taba, Arnon Amir, Deepika Bablani, Peter J. Carlson, Myron D. Flickner, Rajamohan Gandhasri, Guillaume Garreau, Megumi Ito, Jennifer L. Klamo, Jeffrey A. Kusnitz, Nathaniel J. McClatchey, Jeffrey L. McKinstry, Yutaka Y. Nakamura, Tapan K. Nayak, William P. Risk, Kai Schleupen, Ben Shaw 0001, Jay Sivagnaname, Daniel F. Smith, Ignacio Terrizzano, Takanori Ueda, Dharmendra S. Modha. 11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip. In IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024. pages 214-215, IEEE, 2024. [doi]
@inproceedings{CassidyAAAADDEOSTABCFGGIKKMMNNRSSSSTU24,
title = {11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip},
author = {Andrew S. Cassidy and John V. Arthur and Filipp Akopyan and Alexander Andreopoulos and Rathinakumar Appuswamy and Pallab Datta and Michael V. DeBole and Steven K. Esser and Carlos Ortega-Otero and Jun Sawada and Brian Taba and Arnon Amir and Deepika Bablani and Peter J. Carlson and Myron D. Flickner and Rajamohan Gandhasri and Guillaume Garreau and Megumi Ito and Jennifer L. Klamo and Jeffrey A. Kusnitz and Nathaniel J. McClatchey and Jeffrey L. McKinstry and Yutaka Y. Nakamura and Tapan K. Nayak and William P. Risk and Kai Schleupen and Ben Shaw 0001 and Jay Sivagnaname and Daniel F. Smith and Ignacio Terrizzano and Takanori Ueda and Dharmendra S. Modha},
year = {2024},
doi = {10.1109/ISSCC49657.2024.10454451},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454451},
researchr = {https://researchr.org/publication/CassidyAAAADDEOSTABCFGGIKKMMNNRSSSSTU24},
cites = {0},
citedby = {0},
pages = {214-215},
booktitle = {IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024},
publisher = {IEEE},
isbn = {979-8-3503-0620-0},
}