Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool

Luis Castano-Londono, Cristian Alzate-Anzola, David Marquez-Viloria, Guillermo Gallo, Gustavo Osorio. Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool. In Juan Carlos Figueroa García, Mario Duarte-González, Sebastián Jaramillo-Isaza, Alvaro David Orjuela-Cañon, Yesid Díaz Gutierrez, editors, Applied Computer Sciences in Engineering - 6th Workshop on Engineering Applications, WEA 2019, Santa Marta, Colombia, October 16-18, 2019, Proceedings. Volume 1052 of Communications in Computer and Information Science, pages 52-63, Springer, 2019. [doi]

Abstract

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