P. Cenci, M. Bolatkale, R. Rutten, M. Ganzerli, G. Lassche, K. Makinwa, L. Breems. A 3.2mW SAR-assisted CTΔ∑ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS. In 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019. pages 230, IEEE, 2019. [doi]
@inproceedings{CenciBRGLMB19,
title = {A 3.2mW SAR-assisted CTΔ∑ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS},
author = {P. Cenci and M. Bolatkale and R. Rutten and M. Ganzerli and G. Lassche and K. Makinwa and L. Breems},
year = {2019},
doi = {10.23919/VLSIC.2019.8778176},
url = {https://doi.org/10.23919/VLSIC.2019.8778176},
researchr = {https://researchr.org/publication/CenciBRGLMB19},
cites = {0},
citedby = {0},
pages = {230},
booktitle = {2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019},
publisher = {IEEE},
isbn = {978-4-86348-720-8},
}