A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations

Francesco Centurelli, Luca Giancane, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti. A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations. In Nadine Azémard, Lars J. Svensson, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings. Volume 4644 of Lecture Notes in Computer Science, pages 516-525, Springer, 2007. [doi]

Abstract

Abstract is missing.