Noureddine Chabini. A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs. In Nadine Azémard, Lars J. Svensson, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings. Volume 4644 of Lecture Notes in Computer Science, pages 64-74, Springer, 2007. [doi]
Abstract is missing.