An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme

Kwanyeob Chae, JongRyun Choi, Hyungkwon Lee, Jinho Choi, Shinyoung Yi, Yoonjee Nam, Sangyun Hwang, Joohyung Lee, Won Lee, Kihwan Seong, Joohee Shin, Soo-Min Lee, Seokkyun Ko, Jihun Oh, Billy Koo, Sanghune Park, Jongshin Shin, Hyungjong Ko. An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme. In 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019. pages 96, IEEE, 2019. [doi]

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