Kwanyeob Chae, JongRyun Choi, Hyungkwon Lee, Jinho Choi, Shinyoung Yi, Yoonjee Nam, Sangyun Hwang, Joohyung Lee, Won Lee, Kihwan Seong, Joohee Shin, Soo-Min Lee, Seokkyun Ko, Jihun Oh, Billy Koo, Sanghune Park, Jongshin Shin, Hyungjong Ko. An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme. In 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019. pages 96, IEEE, 2019. [doi]
@inproceedings{ChaeCLCYNHLLSSL19,
title = {An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme},
author = {Kwanyeob Chae and JongRyun Choi and Hyungkwon Lee and Jinho Choi and Shinyoung Yi and Yoonjee Nam and Sangyun Hwang and Joohyung Lee and Won Lee and Kihwan Seong and Joohee Shin and Soo-Min Lee and Seokkyun Ko and Jihun Oh and Billy Koo and Sanghune Park and Jongshin Shin and Hyungjong Ko},
year = {2019},
doi = {10.23919/VLSIC.2019.8777959},
url = {https://doi.org/10.23919/VLSIC.2019.8777959},
researchr = {https://researchr.org/publication/ChaeCLCYNHLLSSL19},
cites = {0},
citedby = {0},
pages = {96},
booktitle = {2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019},
publisher = {IEEE},
isbn = {978-4-86348-720-8},
}