Kwanyeob Chae, Billy Koo, Jihun Oh, Sanghune Park, Jongshin Shin, Jaehong Park. Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface. In International SoC Design Conference, ISOCC 2018, Daegu, South Korea, November 12-15, 2018. pages 140-141, IEEE, 2018. [doi]
@inproceedings{ChaeKOPSP18,
title = {Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface},
author = {Kwanyeob Chae and Billy Koo and Jihun Oh and Sanghune Park and Jongshin Shin and Jaehong Park},
year = {2018},
doi = {10.1109/ISOCC.2018.8649918},
url = {https://doi.org/10.1109/ISOCC.2018.8649918},
researchr = {https://researchr.org/publication/ChaeKOPSP18},
cites = {0},
citedby = {0},
pages = {140-141},
booktitle = {International SoC Design Conference, ISOCC 2018, Daegu, South Korea, November 12-15, 2018},
publisher = {IEEE},
isbn = {978-1-5386-7960-9},
}