TLP analysis of 0.125 mum CMOS ESD input protection circuit

Michael Chaine, James Davis, Al Kearney. TLP analysis of 0.125 mum CMOS ESD input protection circuit. Microelectronics Reliability, 45(2):223-231, 2005. [doi]

@article{ChaineDK05,
  title = {TLP analysis of 0.125 mum CMOS ESD input protection circuit},
  author = {Michael Chaine and James Davis and Al Kearney},
  year = {2005},
  doi = {10.1016/j.microrel.2004.05.010},
  url = {http://dx.doi.org/10.1016/j.microrel.2004.05.010},
  tags = {analysis},
  researchr = {https://researchr.org/publication/ChaineDK05},
  cites = {0},
  citedby = {0},
  journal = {Microelectronics Reliability},
  volume = {45},
  number = {2},
  pages = {223-231},
}