Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays - researchr publication

researchr

You are not signed in
Sign in
Sign up

Avik Chakraborty. Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays. In 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India. pages 249-254, IEEE Computer Society, 2005. [doi]

Abstract is missing.

runs on WebDSL