A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real-time image decomposition

Anirban Chakraborty, Ayan Banerjee. A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real-time image decomposition. J. Real-Time Image Processing, 17(5):1421-1446, 2020. [doi]

@article{ChakrabortyB20-2,
  title = {A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real-time image decomposition},
  author = {Anirban Chakraborty and Ayan Banerjee},
  year = {2020},
  doi = {10.1007/s11554-019-00901-x},
  url = {https://doi.org/10.1007/s11554-019-00901-x},
  researchr = {https://researchr.org/publication/ChakrabortyB20-2},
  cites = {0},
  citedby = {0},
  journal = {J. Real-Time Image Processing},
  volume = {17},
  number = {5},
  pages = {1421-1446},
}