Angshuman Chakraborty, Sambhu Nath Pradhan. A technique for power reduction of CMOS circuit at 65nm technology. In 1st International Conference on Recent Advances in Information Technology, RAIT 2012, Dhanbad, India, March 15-17, 2012. pages 576-580, IEEE, 2012. [doi]
@inproceedings{ChakrabortyP12-0,
title = {A technique for power reduction of CMOS circuit at 65nm technology},
author = {Angshuman Chakraborty and Sambhu Nath Pradhan},
year = {2012},
doi = {10.1109/RAIT.2012.6194592},
url = {http://dx.doi.org/10.1109/RAIT.2012.6194592},
researchr = {https://researchr.org/publication/ChakrabortyP12-0},
cites = {0},
citedby = {0},
pages = {576-580},
booktitle = {1st International Conference on Recent Advances in Information Technology, RAIT 2012, Dhanbad, India, March 15-17, 2012},
publisher = {IEEE},
isbn = {978-1-4577-0694-3},
}