A technique for power reduction of CMOS circuit at 65nm technology

Angshuman Chakraborty, Sambhu Nath Pradhan. A technique for power reduction of CMOS circuit at 65nm technology. In 1st International Conference on Recent Advances in Information Technology, RAIT 2012, Dhanbad, India, March 15-17, 2012. pages 576-580, IEEE, 2012. [doi]

Abstract

Abstract is missing.