A CAD approach for on-chip PDN with power and supply noise reduction for multi-voltage SOCS in pre-layout stage

Moumita Chakraborty, Debasri Saha, Amlan Chakrabarti. A CAD approach for on-chip PDN with power and supply noise reduction for multi-voltage SOCS in pre-layout stage. In 7th International Symposium on Embedded Computing and System Design, ISED 2017, Durgapur, India, December 18-20, 2017. pages 1-4, IEEE, 2017. [doi]

Abstract

Abstract is missing.