Prasad R. Chalasani, Krishnaiyan Thulasiraman, M. A. Corneau. Integrated VLSI layout compaction and wire balancing on a shared memory multiprocessor: evaluation of a parallel algorithm. In International Symposium on Parallel Architectures, Algorithms and Networks, ISPAN 1994, Kanazawa, Japan, December 14-16, 1994. pages 49-56, IEEE, 1994. [doi]
Abstract is missing.