A robust multithreaded HDL/ESL simulator for deep submicron integrated circuit designs

Terence Chan. A robust multithreaded HDL/ESL simulator for deep submicron integrated circuit designs. In 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012, Kaohsiung, Taiwan, December 2-5, 2012. pages 416-419, IEEE, 2012. [doi]

Abstract

Abstract is missing.