B. S. Chandrasekhar, S. Deepanjali, Sk. Noor Mahammad. Fault Tolerant Technique for Processor Control Path to Mitigate SEUs in FPGA. In IEEE International Symposium on Smart Electronic Systems, iSES 2022, Warangal, India, December 18-22, 2022. pages 31-35, IEEE, 2022. [doi]
@inproceedings{ChandrasekharDM22,
title = {Fault Tolerant Technique for Processor Control Path to Mitigate SEUs in FPGA},
author = {B. S. Chandrasekhar and S. Deepanjali and Sk. Noor Mahammad},
year = {2022},
doi = {10.1109/iSES54909.2022.00018},
url = {https://doi.org/10.1109/iSES54909.2022.00018},
researchr = {https://researchr.org/publication/ChandrasekharDM22},
cites = {0},
citedby = {0},
pages = {31-35},
booktitle = {IEEE International Symposium on Smart Electronic Systems, iSES 2022, Warangal, India, December 18-22, 2022},
publisher = {IEEE},
isbn = {979-8-3503-9922-6},
}